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ADJD-S371-QR999 miniature surface-mount rgb digital color sensor module data sheet description adjd-s37 -qr999 is a cost efective, 4 channel digital output rgb+clear sensor in miniature surface-mount package with a mere size of 3.9 x 4.5 x .8 mm. it is an ic module with combination of white led and cmos ic with integrated rgb flters + clear channel and analog-to-digital converter front end. it is ideal for applications like color detection, mea - surement, illumination sensing for display backlight adjustment such as colors, contrast and brightness enhancement in mobile devices which demand higher package integration, small footprint and low power consumption. the 2-wire serial output allows direct interface to microcontroller or other logic control for further signal processing without additional component such as analog to digital converter. with the wide sensing range of 00 lux to 00,000 lux, the sensor can be used for many applications with diferent light levels by adjusting the gain setting. additional features include a selectable sleep mode to minimize current con- sumption when the sensor is not in use. features ? four channel integrated light to digital converter (red, green, blue and clear). ? 0 bit digital output resolution ? independent gain selection for each channel ? wide sensitivity coverage: 0. klux - 00 klux ? two wire serial communication ? built in oscillator/selectable external clock ? low power mode (sleep mode) ? small 3.9 x 4.5 x .8 mm module ? integrated solution with sensor, led and separator in module for ease of design ? lead free applications ? mobile appliances ? consumer appliances
2 absolute maximum ratings (sensor) [1, 2] parameter symbol minimum maximum units notes storage temperature t stg_abs -40 85 c digital supply voltage, d vdd to d vss v ddd_abs 2.5 3.6 v analog supply voltage, a vdd to a vss v dda_abs 2.5 3.6 v input voltage v in_abs 2.5 3.6 v all i/o pins human body model esd rating esd hbm_abs 2 kv all pins, human body model per jesd22-a 4 functional block diagram electrical specifcations absolute maximum ratings at t a = 25c (led) parameter symbol minimum maximum units dc forward current i f 0 ma power dissipation 39 mw reverse voltage @ ir = 00 a v r 5 v operating temperature range -20 85 c storage temperature range -40 85 c digit al output adc sampling block led anode clear r g b
3 recommended operating conditions (sensor) parameter symbol minimum typical maximum units free air operating temperature t a 0 25 70 c digital supply voltage, d vdd to d vss v ddd 2.5 2.6 3.6 v analog supply voltage, a vdd to a vss v dda 2.5 2.6 3.6 v output current load high i oh 3 ma output current load low i ol 3 ma input voltage high level [4] v ih 0.7 v ddd v ddd v input voltage low level [4] v il 0 0.3 v ddd v electrical characteristics at t a = 25 c (led) parameter symbol minimum typical maximum units dc forward voltage @ i f = 5 ma v f 2.85 3.35 v reverse breakdown voltage @ i r = 00 a v r 5 v dc electrical specifcations (sensor) over recommended operating conditions (unless otherwise specifed) parameter symbol conditions minimum typical [3] maximum units output voltage high level [5] v oh i oh = 3 ma v ddd - 0.4 v output voltage low level [6] v ol i oh = 3 ma 0.2 v supply current [7] i dd_static (note 8) 3.8 5 ma sleep-mode supply current [7] i dd_slp (note 8) 2 a input leakage current i leak -0 0 a ac electrical specifcations (sensor) over recommended operating conditions (unless otherwise specifed) parameter symbol conditions minimum typical [3] maximum units internal clock frequency f _clk_int 26 mhz external clock frequency f _clk_ext 6 40 mhz 2-wire interface frequency f _2wire 00 khz optical specifcation (sensor) parameter symbol conditions minimum typical [3] maximum units dark ofset v d ee = 0 20 lsb
4 minimum sensitivity [3] parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm refer note 9 b 52 lsb/(mw cm -2 ) l p = 542 nm refer note 0 g 78 l p = 645 nm refer note r 254 l p = 645 nm refer note clear 264 maximum sensitivity [3] parameter symbol conditions minimum typical (note 3) maximum units irradiance responsivity re l p = 460 nm refer note 9 b 3796 lsb/(mw cm -2 ) l p = 542 nm refer note 0 g 4725 l p = 645 nm refer note r 6288 l p = 645 nm refer note clear 6590 saturation irradiance for minimum sensitivity [12] parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm refer note 9 b 6.73 mw/cm 2 l p = 542 nm refer note 0 g 5.74 l p = 645 nm refer note r 4.03 l p = 645 nm refer note clear 3.87
5 saturation irradiance for maximum sensitivity [12] parameter symbol conditions minimum typical (note 3) maximum units saturation irradiance l p = 460 nm refer note 9 b 0.27 mw/cm 2 l p = 542 nm refer note 0 g 0.22 l p = 645 nm refer note r 0.6 l p = 645 nm refer note clear 0.6 notes: . the absolute maximum ratings are those values beyond which damage to the device may occur. the device should not be operated at these limits. the parametric values defned in the electrical specifcations table are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will defne the conditions for actual device operation. 2. unless otherwise specifed, all voltages are referenced to ground. 3. specifed at room temperature (25c) and v ddd = v dda = 2.5 v. 4. applies to all di pins. 5. applies to all do pins. sdaslv go tri-state when output logic high. minimum v oh depends on the pull-up resistor value. 6. applies to all do and dio pins. 7. refers to total device current consumption. 8. output and bidirectional pins are not loaded. 9. test condition is blue light of peak wavelength ( l p ) 460 nm and spectral half width ( l / 2 ) 25 nm. 0. test condition is green light of peak wavelength ( l p ) 542 nm and spectral half width ( l / 2 ) 35 nm. . test condition is red light of peak wavelength ( l p ) 645 nm and spectral half width ( l / 2 ) 20 nm. 2. saturation irradiance = (msb)/(irradiance responsivity). 0 0.2 0.4 0.6 0.8 1.0 400 420 440 460 480 520 540 580 620 640 680 500 560 600 660 700 wavelength (nm) relative sensitivity figure 1. typical spectral response when the gains for all the color channels are set at equal
6 serial interface timing information parameter symbol minimum maximum units scl clock frequency f scl 0 00 khz (repeated) start condition hold time t hd:sta 4 - s data hold time t hd:cat 0 3.45 s scl clock low period t low 4.7 - s scl clock high period t high 4.0 - s repeated start condition setup time t su:sta 4.7 - s data setup time t su:dat 250 - s stop condition setup time t su:std 4.0 - s bus free time between start and stop conditions t buf 4.7 - s figure 2. serial interface bus timing waveforms serial interface reference description the programming interface to the adjd-s37 -qr999 is a 2-wire serial bus. the bus consists of a serial clock (scl) and a serial data (sda) line. the sda line is bi-directional on adjd-s37 -qr999 and must be connected through a pull-up resistor to the positive power supply. when the bus is free, both lines are high. the 2-wire serial bus on adjd-s37 -qr999 requires one device to act as a master while all other devices must be slaves. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. slaves are identifed by unique device addresses. both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. a transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. the adjd-s37 -qr999 serial bus interface always oper - ates as a slave transceiver with a data transfer rate of up to 00kbit/s. start/stop condition the master initiates and terminates all serial data transfers. to begin a serial data transfer, the master must send a unique signal to the bus called a start condition. this is defned as a high to low transition on the sda line while scl is high. t low t hd:dat t hd:sta t su:sto t high t su:dat t hd:sta t buf t su:sta sda scl s sr p s
7 the master terminates the serial data transfer by sending another unique signal to the bus called a stop condition. this is defned as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condition. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are functionally identical. figure 3. start/stop condition data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low. figure 4. data bit transfer scl scl s start condition p stop condition scl sda data valid data change
8 the scl clock line synchronizes the serial data transmis - sion on the sda data line. it is always generated by the master. the frequency of the scl clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. the master by default drives the sda data line. the slave drives the sda data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. the sda data line driven by the master may be implemented on the negative edge of the scl clock line. the master may sample data driven by the slave on the positive edge of the scl clock line. figure shows an example of a master implementation and how the scl clock line and sda data line can be synchronized. figure 5. data bit synchronization a complete data transfer is 8-bits long or -byte. each byte is sent most signifcant bit (msb) frst followed by an acknowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes (depending on the data format). figure 6. data byte transfer scl sda sda data sampled on the positive edge of scl sda data driven on the negative edge of scl sda msb msb lsb lsb ack no ack scl s or sr p sr sr or p 1 2 8 9 1 2 8 9 st art or repeated st art condition stop or repeated st art condition
9 acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave-receiver and master-transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either stop the transfer or generate a repeated start to start a new transfer. figure 7. slave-receiver acknowledge in the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the master can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. figure 8. master-receiver acknowledge scl (master) sda (master-transmitter) sda (slave-receiver) acknowledge acknowledge clock pulse 9 8 lsb sda left high by transmitter sda pulled low by receiver scl (master) sda (slave-transmitter) sda (master-receiver) acknowledge clock pulse not acknowledge 9 p sr 8 lsb sda left high by transmitter sda left high by receiver stop or repeated start condition
0 addressing each slave device on the serial bus needs to have a unique address. this is the frst byte that is sent by the master- transmitter after the start condition. the address is defned as the frst seven bits of the frst byte. the eighth bit or least signifcant bit (lsb) determines the direction of data transfer. a one in the lsb of the frst byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). a zero in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the frst byte and set itself up as a slave-transmitter or slave- receiver depending on the lsb of the frst byte. the slave address on adjd-s37 -qr999 is 0x74 (7-bits). data format adjd-s37 -qr999 uses a register-based programming architecture. each register has a unique address and controls a specifc function inside the chip. to write to a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowledges, the master generates a stop condition to end the data transfer. figure 9. slave addressing figure 10. register byte write protocol a6 a5 a4 a3 a2 a1 a0 1 1 1 0 1 0 0 r/w sla ve address msb lsb s a 6 a 5 a 4 a 3 a 2 a 1 a 0 w a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d7 d6 d5 d4 d3 d2 d1 d0 a p st art condition master will write d ata stop condition master sends sla ve address master writes register address master writes register d ata sla ve acknowledge sla ve acknowledge sla ve acknowledge
to read from a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least signifcant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then acknowledge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. figure 11. register byte read protocol s a 6 a 5 a 4 a 3 a 2 a 1 a 0 w a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a sr a6 a5 a4 a3 a2 a1 a0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p st art condition master will write d ata master will read d ata repea ted st art condition stop condition master sends sla ve address master sends sla ve address master writes register address master reads register d ata sla ve acknowledge sla ve acknowledge sla ve acknowledge master not acknowledge
2 pin name description led -ve led cathode 2 nc no connection 3 led +ve led anode 4 sda bidirectional data pin. a pull-up resistor should be tied to sda because it goes tri-state to output logic 5 dvdd digital power pin 6 scl serial interface clock 7 avdd analog power pin 8 sleep sleep pin. when sleep = , the device goes into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. 9 agnd analog ground pin 0 xrst reset pin. global, asynchronous, active-low system reset. when asserted low, xrst resets all registers. minimum reset pulse low is us and must be provided by external circuitry. dgnd digital ground pin 2 xclk external clock input mechanical drawing sensor pcb light sep ara tor led section a - a 1.80 a a 3.90 4.50 1 12 11 10 9 8 7 6 5 4 2 3 1 2 3 orien ta tion mark 0.80 bottom side led pa d (a t top side) top side (led area) footprint at bottom side 12 4
3 description nominal tolerances body size (w, mm) 3.90 +0.6 body size (l, mm) 4.50 0.2 overall thickness (t, mm) .80 0.2 terminal pitch (mm) 0.8 0.08 figure 13: luminous intensity vs forward current (led) figure 12: forward current vs forward voltage (led) refow profle it is recommended that henkel pb-free solder paste lf3 0 be used for soldering adjd-s37 -qr999. below is the recommended refow profle. del ta cooling = 2 c/sec. max. del ta flux = 2 c/sec. max. del ta ram p = 1 c/sec. max. t pre = 40 to 60 sec. max. t reflow = 20 to 40 sec. max. t peak 230 5 c t reflow 218 c t ma x 160 c t mi n 120 c
4 recommended land pattern (on customer board) recommended aperture dimensions with respect to mounting axis on customer board 2.20 2.10 5.00 3.00 0.80 (12x) 0.50 (12x) 2.10 1.60 2.40 4.40 r 0.50 min ? 4.50 window/ boundary for obst acle-free light pa th land pa ttern (on customer board) min. 2.90 center of the footprint
5 recommendations for handling and storage of ADJD-S371-QR999 this product is qualifed as moisture sensitive level 3 per jedec j-std-020. precautions when handling this moisture sensitive product is important to ensure the reliability of the product. do refer to avago application note an5305 handling of moisture sensitive surface mount devices for details. a. storage before use - unopened moisture barrier bag (mbb) can be stored at 30c and 90% rh or less for maximum year. - it is not recommended to open the mbb prior to assembly (e.g., for iqc). - it should also be sealed with a moisture absorbent material (silica gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag. b. control after opening the mbb - the humidity indicator card (hic) shall be read immediately upon opening of mbb. - the components must be kept at <30c/60% rh at all time and all high temperature related process including soldering, curing or rework need to be completed within 68 hrs. c. control for unfnished reel - for any unused components, they need to be stored in sealed mbb with desiccant or desiccator at <5% rh. d. control of assembled boards - if the pcb soldered with the components is to be subjected to other high temperature processes, the pcb need to be stored in sealed mbb with desiccant or desiccator at <5% rh to ensure no components have exceeded their foor life of 68 hrs. e. baking is required if: - 0% or 5% hic indicator turns pink. - the components are exposed to condition of >30c/60% rh at any time. - the components foor life exceeded 68 hrs. - recommended baking condition (in component form): 25c for 24 hrs.
6 package tape and reel dimensions reel dimensions carrier tape dimensions notes: . ao measured at 0.3mm above base of pocket 2. 0 pitches cumulative tolerance is 0.2mm 3. dimensions are in millimeters (mm) (f)5.500.05 (e1)1.750.10 (w)12.000.10 (p2)2.000.05 (po)4.000.10 (p1)8.000.10 (t)0.300.05 (ko)1.950.10 ?1.50 0.00 0.10 (ao)4.200.10 r0.50 ?1.50 min (ref 1.50) (ref 0.75) note: . dimensions are in milimeters (mm)
7 appendix a: typical application diagram buffer led driver 10k 10k 10k 10k host system xrst sda scl xrst sda scl sleep xclk led +ve led -v e external oscilla tor if external clock mode is selected dvdd vol t age regula tor vol t age regula tor dvdd dgnd a vdd host system decoupling cap acitor (100 nf) decoupling cap acitor (100 nf) agnd color sensor module note: it is recommended to drive the led with dc current at i f = 5ma
8 appendix b: sensor register list
9 1) ctrl: control register b7 b6 b5 b4 b3 b2 b b0 n/a gofs gssr n/a not available. gssr get sensor reading. active high and automatically cleared. result is stored in registers 64-7 (dec). gofs get ofset reading. active high and automatically cleared. result is stored in registers 72-75 (dec). 2) config: confguration register b7 b6 b5 b4 b3 b2 b b0 n/a cap_red[3:0] b7 b6 b5 b4 b3 b2 b b0 n/a extckl sleep tofs n/a not available. extclk external clock mode. active high. sleep sleep mode. active high and external clock mode only. automatically cleared if otherwise. tofs trim ofset mode. active high. b7 b6 b5 b4 b3 b2 b b0 n/a cap_green[3:0] 3) cap_red: capacitor settings register for red channel n/a not available. cap_red number of red channel capacitors. n/a not available. cap_blue number of blue channel capacitors. 4) cap_green: capacitor settings register for green channel n/a not available. cap_green number of green channel capacitors. 5) cap_blue: capacitor settings register for blue channel b7 b6 b5 b4 b3 b2 b b0 n/a cap_blue[3.0]
20 n/a not available. cap_clear number of clear channel capacitors. 6) cap_clear: capacitor settings register for clear channel b7 b6 b5 b4 b3 b2 b b0 n/a cap_clear[3:0] int_red number of red channel integration time slots. 7) int_red: integration time slot setting register for red channel b7 b6 b5 b4 b3 b2 b b0 cap_red[7:0] b7 b6 b5 b4 b3 b2 b b0 n/a int_red[:8] int_green number of green channel integration time slots. 8) int_green: integration time slot setting register for green channel b7 b6 b5 b4 b3 b2 b b0 int_green[7:0] b7 b6 b5 b4 b3 b2 b b0 n/a int_green[:8] int_blue number of blue channel integration time slots. 9) int_blue: integration time slot setting register for blue channel b7 b6 b5 b4 b3 b2 b b0 int_blue[7:0] b7 b6 b5 b4 b3 b2 b b0 n/a int_blue[ :8]
2 int_clear number of clear channel integration time slots. 10) int_clear: integration time slot setting register for clear channel b7 b6 b5 b4 b3 b2 b b0 int_clear[7:0] b7 b6 b5 b4 b3 b2 b b0 n/a int_clear[:8] data_red red channel adc data. 11) data_red_lo: low byte register of red channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 data_red[7:0] n/a not available. data_red red channel adc data. 12) data_red_hi: high byte register of red channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 n/a data_red[9:8] data_green green channel adc data. 13) data_green_lo: low byte register of green channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 data_green[7:0] n/a not available. data_green green channel adc data. 14) data_green_hi: high byte register of green channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 n/a data_green[9:8]
22 data_blue blue channel adc data. 15) data_blue_lo: low byte register of blue channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 data_blue[7:0] n/a not available. data_blue blue channel adc data. 16) data_blue_hi: high byte register of blue channel sensor adc reading data_clear clear channel adc data. 17) data_clear_lo: low byte register of clear channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 data_clear[7:0] n/a not available. data_clear clear channel adc data. 18) data_clear_hi: high byte register of clear channel sensor adc reading b7 b6 b5 b4 b3 b2 b b0 n/a data_clear[9:8] b7 b6 b5 b4 b3 b2 b b0 n/a data_blue[9:8] 19) offset_red: ofset data register for red channel b7 b6 b5 b4 b3 b2 b b0 sign_red offset_red[6:0] sign_red sign bit. 0 = positive, = negative. offset_red red channel adc ofset data.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. av02-0314en - july 24, 2007 20) offset_green: ofset data register for green channel b7 b6 b5 b4 b3 b2 b b0 sign_green offset_green[6:0] sign_green sign bit. 0 = positive, = negative. offset_green green channel adc ofset data. 21) offset_blue: ofset data register for blue channel b7 b6 b5 b4 b3 b2 b b0 sign_blue offset_blue[6:0] sign_blue sign bit. 0 = positive, = negative. offset_blue blue channel adc ofset data. 22) offset_clear: ofset data register for clear channel b7 b6 b5 b4 b3 b2 b b0 sign_clear offset_clear[6:0] sign_clear sign bit. 0 = positive, = negative. offset_clear clear channel adc ofset data.

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